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--- wrtu54g-tm:jtag [2010/11/09 12:10] – neutronscott
+++ wrtu54g-tm:jtag [2023/11/04 22:30] (current) – external edit 127.0.0.1
@@ Line 6: / Line 6: @@
 For visual: [[http://wrt.scottn.us/jtag-diagram.jpg|diagram]] [[http://wrt.scottn.us/poor-man-jtag.jpg|mine]]
-So I tried tjtag again and no dice. wtf. but some italian program for AR7 noticed the CPU ID as "1" so I searched and found [[http://urjtag.sourceforge.net/|UrJTAG]]. First **cable dlc5 parallel 0x378** then **detect** then **include admtek/adm5120/adm5120** and finally you should be able to use **flashmem 0x3cf00000 uboot.bin**. Of course, this is after you find libusb0.dll and ftd25xx.dll so the program will run. Neither library being utilized... wtf! But works better than getting cygwin for the old jtag tools ports.. It's flashing now, an hour later 64kb is done. I'll re-write this if it works.. I'm going to bed. What a day! All to save a $15 router. hah.
+So I tried tjtag again and no dice. wtf. but some italian program for AR7 noticed the CPU ID as "1" so I searched and found [[http://urjtag.sourceforge.net/|UrJTAG]]. I had to find libusb0.dll and ftd25xx.dll so the program will run. Neither library being utilized... wtf! But works better than getting cygwin for the old jtag tools ports.. What a day! All to save a $15 router. hah.
-so i woke up and no dice. i programmed the 8-bit address. soooo unless UrJtag says the Manufacturer and Chip type, it's not gonna work. Remember that. I assumed it was a supported family, but unsupported chip and thus didn't display. it's programming again now, and i'm going to work. **0x3fc00000** would be the 16-bit access to any MIPS CPU's boot-rom, which is of course mapped to flash for us. It's also mapped at 0x30000000 and maybe a few other places ... :P
+I returned from sleep and it didn't work. I programmed the wrong address. soooo unless UrJtag says the Manufacturer and Chip type, it's not gonna work. Remember that. I assumed it was a supported family, but unsupported chip and thus didn't display. **0x3fc00000** would be the 16-bit access to any MIPS CPU's boot-rom, which is of course mapped to flash for us. It's also mapped at 0x30000000. For me, the 64k image takes just under 30minutes to flash. I recommend using **noverify** when flashing.
+<code>
+C:\Program Files\UrJTAG>jtag.exe
+UrJTAG 0.10 #1502
+Copyright (C) 2002, 2003 ETC s.r.o.
+Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors
+UrJTAG is free software, covered by the GNU General Public License, and you are
+welcome to change it and/or distribute copies of it under certain conditions.
+There is absolutely no warranty for UrJTAG.
+WARNING: UrJTAG may damage your hardware!
+Type "quit" to exit, "help" for help.
+jtag> cable dlc5 parallel 0x378
+Initializing parallel port at 0x378
+jtag> detect
+IR length: 5
+Chain length: 1
+Device Id: 00000000000000000000000000000001 (0x0000000000000001)
+  Unknown manufacturer!
+chain.c(149) Part 0 without active instruction
+chain.c(200) Part 0 without active instruction
+chain.c(149) Part 0 without active instruction
+jtag> include admtek/adm5120/adm5120
+ImpCode=01000001010000000100000000000000 41404000
+EJTAG version: 2.6
+EJTAG Implementation flags: R4k DINTsup ASID_8 NoDMA MIPS32
+Processor entered Debug Mode.
+jtag> detectflash 0x3fc00000
+Query identification string:
+        Primary Algorithm Command Set and Control Interface ID Code: 0x0002 (AMD/Fujitsu Standard Command Set)
+        Alternate Algorithm Command Set and Control Interface ID Code: 0x0000 (null)
+Query system interface information:
+        Vcc Logic Supply Minimum Write/Erase or Write voltage: 2700 mV
+        Vcc Logic Supply Maximum Write/Erase or Write voltage: 3600 mV
+        Vpp [Programming] Supply Minimum Write/Erase voltage: 0 mV
+        Vpp [Programming] Supply Maximum Write/Erase voltage: 0 mV
+        Typical timeout per single byte/word program: 16 us
+        Typical timeout for maximum-size multi-byte program: 0 us
+        Typical timeout per individual block erase: 1024 ms
+        Typical timeout for full chip erase: 0 ms
+        Maximum timeout for byte/word program: 512 us
+        Maximum timeout for multi-byte program: 0 us
+        Maximum timeout per individual block erase: 16384 ms
+        Maximum timeout for chip erase: 0 ms
+Device geometry definition:
+        Device Size: 8388608 B (8192 KiB, 8 MiB)
+        Flash Device Interface Code description: 0x0002 (x8/x16)
+        Maximum number of bytes in multi-byte program: 1
+        Number of Erase Block Regions within device: 2
+        Erase Block Region Information:
+                Region 0:
+                        Erase Block Size: 8192 B (8 KiB)
+                        Number of Erase Blocks: 8
+                Region 1:
+                        Erase Block Size: 65536 B (64 KiB)
+                        Number of Erase Blocks: 127
+Primary Vendor-Specific Extended Query:
+        Major version number: 1
+        Minor version number: 1
+        Address Sensitive Unlock: Required
+        Erase Suspend: Read/write
+        Sector Protect: 4 sectors per group
+        Sector Temporary Unprotect: Not supported
+        Sector Protect/Unprotect Scheme: 29BDS640 mode (Software Command Locking)
+        Simultaneous Operation: Not supported
+        Burst Mode Type: Supported
+        Page Mode Type: Not supported
+        ACC (Acceleration) Supply Minimum: 11500 mV
+        ACC (Acceleration) Supply Maximum: 12500 mV
+        Top/Bottom Sector Flag: Bottom boot device
+jtag> flashmem 0x3fc00000 u-boot.img noverify
+Chip: AMD Flash
+        Manufacturer: Macronix
+        Chip: MX29LV640B
+        Protected: 0000
+program:
+flash_unlock_block 0x3FC00000 IGNORE
+block 0 unlocked
+flash_erase_block 0x3FC00000
+flash_erase_block 0x3FC00000 DONE
+erasing block 0: 0
+addr: 0x3FC01000
+</code>